DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 229

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–111. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V
LVCMOS
2.5 V
1.8 V
1.5 V
1.2 V
Standard
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EP3SE80 I/O Timing Parameters
Table 1–111
EP3SE80 devices for single-ended I/O standards.
Table 1–111
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-1.054
-1.307
-1.054
-1.307
-1.065
-1.318
-1.065
-1.318
-1.060
-1.313
-1.082
-1.335
-1.072
-1.325
-1.020
-1.273
1.195
1.605
1.195
1.605
1.206
1.616
1.206
1.616
1.201
1.611
1.225
1.635
1.215
1.625
1.163
1.573
Fast Model
through
lists the EP3SE80 column pins input timing parameters for single-ended
Commercial
-1.054
-1.307
-1.054
-1.307
-1.065
-1.318
-1.065
-1.318
-1.060
-1.313
-1.082
-1.335
-1.072
-1.325
-1.020
-1.273
1.195
1.605
1.195
1.605
1.206
1.616
1.206
1.616
1.201
1.611
1.225
1.635
1.215
1.625
1.163
1.573
Table 1–114
-1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173
-1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661
-1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173
-1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661
-1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172
-1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660
-1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172
-1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660
-1.513 -1.650 -1.890 -1.837 -2.191 -1.650 -1.890 -1.837 -2.191
-1.878 -2.042 -2.339 -2.232 -2.679 -2.042 -2.339 -2.232 -2.679
-1.553 -1.686 -1.888 -1.835 -2.189 -1.686 -1.888 -1.835 -2.189
-1.918 -2.078 -2.337 -2.230 -2.677 -2.078 -2.337 -2.230 -2.677
-1.530 -1.654 -1.818 -1.765 -2.119 -1.654 -1.818 -1.765 -2.119
-1.895 -2.046 -2.267 -2.160 -2.607 -2.046 -2.267 -2.160 -2.607
-1.453 -1.555 -1.662 -1.609 -1.963 -1.555 -1.662 -1.609 -1.963
-1.818 -1.947 -2.111 -2.004 -2.451 -1.947 -2.111 -2.004 -2.451
1.704
2.302
1.704
2.302
1.703
2.301
1.703
2.301
1.712
2.310
1.752
2.350
1.729
2.327
1.652
2.250
1.1 V
V
C2
CCL
=
list the maximum I/O timing parameters for
1.861
2.513
1.861
2.513
1.863
2.515
1.863
2.515
1.875
2.527
1.911
2.563
1.879
2.531
1.780
2.432
1.1 V
V
C3
CCL
=
2.117
2.858
2.117
2.858
2.116
2.857
2.116
2.857
2.135
2.876
2.133
2.874
2.063
2.804
1.907
2.648
1.1 V
V
C4
CCL
=
2.050
2.721
2.050
2.721
2.049
2.720
2.049
2.720
2.068
2.739
2.066
2.737
1.996
2.667
1.840
2.511
1.1 V
V
CCL
=
C4L
2.409
3.186
2.409
3.186
2.408
3.185
2.408
3.185
2.427
3.204
2.425
3.202
2.355
3.132
2.199
2.976
0.9 V
V
CCL
Stratix III Device Handbook, Volume 2
=
1.861
2.513
1.861
2.513
1.863
2.515
1.863
2.515
1.875
2.527
1.911
2.563
1.879
2.531
1.780
2.432
1.1 V
V
CCL
I3
=
2.117
2.858
2.117
2.858
2.116
2.857
2.116
2.857
2.135
2.876
2.133
2.874
2.063
2.804
1.907
2.648
1.1 V
V
I4
CCL
=
2.050
2.721
2.050
2.721
2.049
2.720
2.049
2.720
2.068
2.739
2.066
2.737
1.996
2.667
1.840
2.511
1.1 V
V
CCL
1–229
=
I4L
2.409
3.186
2.409
3.186
2.408
3.185
2.408
3.185
2.427
3.204
2.425
3.202
2.355
3.132
2.199
2.976
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns