DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 228

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–228
Table 1–109. EP3SE50 Column Pin Delay Adders for Regional Clock
Table 1–110. EP3SE50 Row Pin Delay Adders for Regional Clock
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output
adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Parameter
Parameter
Table 1–109
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–109
in Stratix III devices.
Industrial
Table 1–110
Stratix III devices.
-0.001
-0.116
0.152
1.647
Industrial
-0.116
-0.137
0.113
Fast Model
0.13
Fast Model
Commercial
-0.001
-0.119
and
lists the EP3SE50 column pin delay adders when using the regional clock
0.164
1.684
lists the EP3SE50 row pin delay adders when using the regional clock in
Commercial
-0.129
-0.143
0.125
Table 1–110
0.14
-0.003
-0.134
1.1 V
V
0.22
2.61
C2
CCL
=
-0.186 -0.202 -0.218 -0.209
-0.193 -0.214 -0.236 -0.225 -0.295 -0.215 -0.237 -0.226 -0.297
0.182
0.213
1.1 V
V
C2
CCL
list the EP3SE50 regional clock (RCLK) adder values that
=
-0.004
-0.136
0.237
2.926
1.1 V
V
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
C3
CCL
=
0.197
0.241
1.1 V
V
C3
CCL
=
-0.004
3.238
-0.17
1.1 V
V
0.25
C4
CCL
0.212
0.267
1.1 V
=
V
C4
CCL
=
-0.004
-0.171
0.244
3.084
1.1 V
V
CCL
0.205
0.255
1.1 V
V
=
CCL
C4L
=
C4L
-0.006
-0.249
3.298
0.9 V
V
0.31
CCL
0.274
0.385
-0.28
0.9 V
V
CCL
=
=
© July 2010 Altera Corporation
-0.003
-0.131
2.943
1.1 V
V
0.24
-0.206 -0.221 -0.214 -0.283
0.201
0.244
1.1 V
V
I3
CCL
CCL
I3
=
=
-0.004
0.254
3.254
-0.13
0.215
1.1 V
V
1.1 V
V
0.27
CCL
I4
CCL
I4
=
=
I/O Timing
-0.004
0.256
1.1 V
0.246
3.098
V
0.21
-0.13
1.1 V
V
CCL
CCL
=
=
I4L
I4L
0.275
0.386
0.9 V
V
-0.006
-0.216
0.312
3.374
0.9 V
V
CCL
CCL
=
=
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns