DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 165

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–86. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 2)
© July 2010 Altera Corporation
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V
HSTL CLASS I
DIFFERENTIAL
1.5-V
HSTL CLASS I
I/O Standard
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–86
standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-1.332
-0.581
-1.332
-0.581
-1.332
-0.581
-1.137
-0.783
-1.137
-0.783
-1.146
-0.774
-1.146
-0.774
1.476
0.869
1.476
0.869
1.476
0.869
1.274
1.064
1.274
1.064
1.283
1.055
1.283
1.055
Fast Model
lists the EP3SL200 row pins input timing parameters for differential I/O
Commercial
-1.401
-0.578
-1.401
-0.578
-1.401
-0.578
-1.216
-0.772
-1.216
-0.772
-1.228
-0.760
-1.228
-0.760
1.563
0.886
1.563
0.886
1.563
0.886
1.369
1.071
1.369
1.071
1.381
1.059
1.381
1.059
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565
1.994
1.991
1.994
1.991
1.994
1.991
2.088
1.866
2.088
1.866
2.097
1.857
2.097
1.857
1.1 V
V
C2
CCL
=
1.939
2.205
1.939
2.205
1.939
2.205
2.122
1.981
2.122
1.981
2.132
1.971
2.132
1.971
1.1 V
V
C3
CCL
=
2.157
2.405
2.157
2.405
2.157
2.405
2.297
2.216
2.297
2.216
2.313
2.200
2.313
2.200
1.1 V
V
C4
CCL
=
2.071
2.282
2.071
2.282
2.071
2.282
2.206
2.098
2.206
2.098
2.222
2.082
2.222
2.082
1.1 V
V
CCL
=
C4L
2.526
2.297
2.526
2.297
2.526
2.297
2.656
2.118
2.656
2.118
2.672
2.102
2.672
2.102
0.9 V
V
CCL
Stratix III Device Handbook, Volume 2
=
1.934
2.252
1.934
2.252
1.934
2.252
2.156
1.985
2.156
1.985
2.165
1.976
2.165
1.976
1.1 V
V
I3
CCL
=
2.145
2.458
2.145
2.458
2.145
2.458
2.330
2.221
2.330
2.221
2.346
2.205
2.346
2.205
1.1 V
V
CCL
I4
=
2.071
2.282
2.071
2.282
2.071
2.282
2.206
2.098
2.206
2.098
2.222
2.082
2.222
2.082
1.1 V
V
CCL
1–165
=
I4L
2.526
2.297
2.526
2.297
2.526
2.297
2.656
2.118
2.656
2.118
2.672
2.102
2.672
2.102
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns