DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 207

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–102. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3)
© July 2010 Altera Corporation
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
Standard
I/O
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-0.902
-0.697
-0.902
-0.697
-0.896
-0.703
-0.896
-0.703
-0.902
-0.697
-0.902
1.009
0.867
1.015
0.946
1.015
0.946
1.009
0.952
1.009
0.952
1.015
0.946
1.015
Fast Model
Commercial
-0.937
-0.689
-0.937
-0.689
-0.926
-0.700
-0.926
-0.700
-0.937
-0.689
-0.937
1.009
0.912
1.063
0.949
1.063
0.949
1.052
0.960
1.052
0.960
1.063
0.949
1.063
-1.308 -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622
-1.308
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932
-1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942
1.600
1.491
1.600
1.491
1.491
1.491
1.491
1.491
1.597
1.494
1.597
1.494
1.491
1.600
1.491
1.500
1.1 V
V
C2
CCL
=
-1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571
-1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622
-1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571
-1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622
-1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571
1.416
1.910
1.416
1.910
1.816
1.640
1.816
1.640
1.641
1.815
1.641
1.654
1.1 V
V
C3
CCL
=
1.541
2.142
1.541
2.142
1.931
1.888
1.931
1.888
1.891
1.928
1.891
1.906
1.1 V
V
C4
CCL
=
1.476
2.025
1.476
2.025
1.813
1.819
1.813
1.819
1.822
1.810
1.822
1.837
1.1 V
V
CCL
=
C4L
1.748
2.053
1.748
2.053
1.843
2.111
1.843
2.111
2.114
1.840
2.114
2.129
0.9 V
V
Stratix III Device Handbook, Volume 2
CCL
=
1.435
1.908
1.435
1.908
1.809
1.667
1.809
1.667
1.666
1.810
1.666
1.675
1.1 V
V
I3
CCL
=
1.557
2.141
1.557
2.141
1.936
1.903
1.936
1.903
1.908
1.931
1.908
1.918
1.1 V
V
I4
CCL
=
1.494
2.023
1.494
2.023
1.818
1.836
1.818
1.836
1.841
1.813
1.841
1.851
1.1 V
1–207
V
CCL
=
I4L
1.786
2.100
1.786
2.100
1.895
2.144
1.895
2.144
2.149
1.890
2.149
2.159
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns