DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 33

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
© July 2010 Altera Corporation
5. Compare the results of steps 2 and 4. The increase or decrease in delay must be
The Quartus II software reports the timing with the conditions listed in
using
the output timing of the Quartus II software.
Figure 1–6. Output Delay Timing Report Setup for Single-Ended Outputs and Dedicated Differential
Outputs
Note to
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
Figure 1–7
the Quartus II software for differential outputs with single and multiple external
resistors, respectively.
Figure 1–7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor
Figure 1–8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
must be accounted for with IBIS model simulations.
Figure
Equation 1–1 on page
(Note 1)
and
1–6:
Figure 1–8
Output
Buffer
V
GND
CCIO
Output
show the circuit that is represented by the output timing of
Differential Outputs
Differential Outputs
Non-Dedicated
Non-Dedicated
1–7.
V
MEAS
Figure 1–6
R
S
V
V
V
V
V
GND
MEAS
MEAS
MEAS
MEAS
TT
R
C
shows the circuit that is represented by
T
L
R
R
S
S
R
R
P
P
R
R
D
Stratix III Device Handbook, Volume 2
D
Output
Output
p
n
R
D
Table 1–37
1–33