XE8000EV108 Semtech, XE8000EV108 Datasheet - Page 131

• Manufacturer Part Number: XE8000EV108
• Description: EVAL BOARD FOR XE8806/XE8807
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV108

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC06AMI026
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

When the capture function is active, the A and B counters can either upcount or downcount. They do not count
circularly: they restart at zero or at the maximal value (either 0xFF when not cascaded or 0xFFFF when cascaded)
when respectively an overflow or an underflow condition occurs in the counting. The capture function is also active
on the counters when used to generate PWM signals.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 17-15 shows the capture condition as a function of the setting of these
configuration bits.
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective
capture condition occurred. When the counters A and B are not cascaded and do not operate on the same clock,
the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at different
moments. In this case, the processor should read the shadow register associated to a counter only if
interruption related to this counter has been detected.
An edge is detected on the capture signals only if the minimal pulse widths of these signals in the low and high
states are higher than a period of the counter clock source.
17.12 Specifications
© Semtech 2006
CapSel(1:0)
Pulse width in the low and high states for
an external clock source, frequency
division by 2 disabled
Pulse width in the low and high states for
an external clock source, frequency
division by 2 enabled
Pulse width of external capture signals
11
10
01
00
Selected capture signal
Parameter
16 K
PA3
PA2
1 K
Table 17-16: Timing specifications for the counters
Table 17-15: Capture condition selection
CapFunc
17-10
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
fckcnt
Min
500
125
100
25
1
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Selected condition
Typ
Max
XE8806A/XE8807A
Unit
ns
ns
ns
ns
s
-
1 K rising edge
1 K falling edge
2 K
-
16 K rising edge
16 K falling edge
32 K
-
PA3 rising edge
PA3 falling edge
PA3 both edges
-
PA2 rising edge
PA2 falling edge
PA2 both edges
Capture condition
Conditions
@ 1.2V
@ 2.4V
@ 1.2V
@ 2.4V
www.semtech.com
the