XE8000EV108 Semtech, XE8000EV108 Datasheet - Page 32

• Manufacturer Part Number: XE8000EV108
• Description: EVAL BOARD FOR XE8806/XE8807
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV108

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC06AMI026
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.1
5.1.1
The XE8000 chips have three operating modes. These are the normal, low current and very low current modes
(see Figure 5-1). The different modes are controlled by the reset and clock blocks (see the documentation of the
respective blocks).
5.2
Start-up
All bits are reset in the design when a POR or padnreset is active.
RC is enabled, Xtal is disabled and CPU is reset (pmaddr = 0000).
If the port A is used to return from the sleep mode, all bits with nresetcold do not change (see sleep mode)
Start-up
All bits with nresetglobal and nresetpconf(if enabled) are reset. Clock configuration doesn’t change except cpuck
(freqdiv is reset, see clock block). CPU is reset
Active mode
This is the mode where the CPU and all peripherals can work and execute the embedded software.
Standby mode
Executing a HALT instruction moves the XE8000 into the Standby mode. The CPU is stopped, but the clocks
remain active. Therefore, the enabled peripherals remain active e.g. for time keeping. A reset or an interrupt/event
request (if enabled) cancels the standby mode.
Sleep mode
This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks
remain active. No time-keeping is possible. Two instructions are necessary to move into sleep mode. First, the
SleepEn (sleep enable) bit in RegSysCtrl has to be set to 1. The sleep mode can then be activated by setting the
Sleep bit in RegSysReset to 1.
There are three possibe ways to wake-up from the sleep mode:
Note: If the Port A is used to return from the sleep mode, all bits with nresetcold do not change (RegSysCtrl,
Note: It is recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode
© Semtech 2006
Features
Operating mode
RegSysReset (except bit sleep), Enextclock and Biasrc in RegSysClock, RegSysRcTrim1 and
RegSysRcTrim2). The SleepFlag bit in RegSysReset, reads back a 1 if the circuit was in sleep mode
since the flag was last cleared (see reset block for more details).
because this instruction can be executed when the sleep mode is left using the resetfromportA.
1. The POR (power-on-reset caused by a power-down followed by power-on). The RAM information is
2. The padnreset
3. The Port A reset combination (if the Port A is present in the product). See Port A documentation for
Overview
lost.
more details.
5-2
XE8806A/XE8807A
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