XE8000EV108 Semtech, XE8000EV108 Datasheet - Page 55

• Manufacturer Part Number: XE8000EV108
• Description: EVAL BOARD FOR XE8806/XE8807
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV108

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC06AMI026
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRISC interrupt in the CoolRISC stat register. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number
of the highest priority set (its value is 0xFF when no interrupt is memorized). RegIrqIrq indicates the priority level of
the currently activated interrupts.
All interrupt sources are sampled by the highest frequency in the system. A CPU interruption is generated and
memorized when an interrupt becomes high. Between the rising edge of the interrupt on the peripheral and the
rising edge on the CoolRISC core, there is a latency of one clock cycle.
8.5
This chapter describes an example of the software used for the interrupt handler. This software is present by
default in the software development environments. It represents only one of several possible ways of handling the
interrupts.
© Semtech 2006
Interrupt handling software
RegIrqHig
RegIrqEnHig
stat
IE2
7
7
Figure 8-1. Principle of the interrupt handler.
IE1
6
6
GIE
5
5
RegIrqLow RegIrqMid
IN2
8-5
…
4
4
IN1
3
…
3
IN0
2
2
EV1
1
1
XE8806A/XE8807A
EV0
0
0
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