DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 119

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

18.0
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.
FIGURE 18-1:
© 2010 Microchip Technology Inc.
Note:
UxTX
Note:
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
x = 1 or 2
dsPIC30F3010 only has UART1.
UART TRANSMITTER BLOCK DIAGRAM
Internal Data Bus
UTXBRK
Data
Parity
‘0’ (Start)
‘1’ (Stop)
Generator
Parity
Write
UTX8
Transmit Shift Register (UxTSR)
UxTXREG Low Byte
18.1
The key features of the UART module are:
• Full-duplex, 8 or 9-bit data communication
• Even, odd or no parity options (for 8-bit data)
• One or two Stop bits
• Fully integrated Baud Rate Generator with 16-bit
• Baud rates range from 38 bps to 1.875 Mbps at a
• 4-word deep transmit data buffer
• 4-word deep receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt only on address detect
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
prescaler
30 MHz instruction rate
(9th bit = 1)
dsPIC30F3010/3011
Load TSR
UART Module Overview
16 Divider
Write
Control
Signals
Control and Status bits
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Transmit Control
16x Baud Clock
from Baud Rate
Generator
DS70141F-page 119
UxTXIF