DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 125

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

TABLE 18-1:
TABLE 18-2:
SFR Name Addr.
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
Note 1:
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
Note 1:
Name
SFR
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
020C
020E
Addr.
021C
0210
0212
0214
0216
0218
021A
021E
UARTEN
UTXISEL
UARTEN
UTXISEL
UART1 REGISTER MAP
UART2 REGISTER MAP
Bit 15
Bit 15
—
—
—
—
Bit 14
Bit 14
—
—
—
—
—
—
—
—
USIDL
Bit 13
USIDL
Bit 13
—
—
—
—
—
—
Bit 12
Bit 12
—
—
—
—
—
—
—
—
UTXBRK UTXEN UTXBF
(1)
(1)
UTXBRK UTXEN
Bit 11
Bit 11
—
—
—
—
—
—
(NOT AVAILABLE ON dsPIC30F3010)
Bit 10
Bit 10
ALTIO
—
—
—
—
—
Bit 9
UTXBF
—
—
—
Bit 9
—
—
—
Baud Rate Generator Prescaler
Baud Rate Generator Prescaler
TRMT
URX8
UTX8
Bit 8
TRMT
—
UTX8
URX8
Bit 8
—
URXISEL1 URXISEL0 ADDEN
URXISEL1 URXISEL0 ADDEN RIDLE
WAKE
Bit 7
WAKE
Bit 7
LPBACK
LPBACK
Bit 6
Bit 6
ABAUD
Bit 5
ABAUD
Bit 5
Transmit Register
Receive Register
Transmit Register
Receive Register
RIDLE
Bit 4
Bit 4
—
—
PERR
PERR
Bit 3
Bit 3
—
—
PDSEL1 PDSEL0
PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
FERR
Bit 2
FERR
Bit 2
OERR
OERR
Bit 1
Bit 1
URXDA 0000 0001 0001 0000
URXDA 0000 0001 0001 0000
STSEL 0000 0000 0000 0000
Bit 0
Bit 0
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
Reset State