DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 151

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR.
The SLEEP status bit in RCON register is set upon
wake-up.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the SLEEP
status bit. In a POR, the SLEEP bit is cleared.
If the Watchdog Timer is enabled, then the processor
will wake-up from Sleep mode upon WDT time-out. The
SLEEP and WDTO status bits are both set.
20.5.2
In Idle mode, the clock to the CPU is shut down while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module
that allows them to operate during Idle.
The LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• On any interrupt that is individually enabled (i.e.,
• On any Reset (POR, BOR, MCLR)
• On a WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAV instruction.
© 2010 Microchip Technology Inc.
Note:
bit is ‘1’) and meets the required priority level
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency crys-
tals). In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the clock failure trap,
the FRC oscillator will be enabled, and the
user will have to re-enable the crystal
oscillator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable, and will
remain in Sleep until the oscillator clock
has started.
IDLE MODE
LOCK
and T
PWRT
), the crystal oscillator
POR
,
Any interrupt that is individually enabled (using the IE
bit) and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The IDLE status bit in
the RCON register is set upon wake-up.
Any Reset, other than POR, will set the IDLE status bit.
On a POR, the IDLE bit is cleared.
If the Watchdog Timer is enabled, then the processor
will wake-up from Idle mode upon WDT time-out. The
IDLE and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
20.6
The Configuration bits in each device Configuration
register specify some of the device modes and are pro-
grammed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are five device
Configuration registers available to the user:
1.
2.
3.
4.
5.
The placement of the Configuration bits is automati-
cally handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For
additional information, please refer to the programming
specifications of the device.
Note:
dsPIC30F3010/3011
FOSC (0xF80000): Oscillator Configuration
register
FWDT (0xF80002): Watchdog Timer
Configuration register
FBORPOR (0xF80004): BOR and POR
Configuration register
FGS (0xF8000A): General Code Segment
Configuration register
FICD (0xF8000C): Debug Configuration
Register
Device Configuration Registers
If the code protection Configuration bits
(FGS<GCP> and FGS<GWRP>) have
been programmed, an erase of the entire
code-protected device is only possible at
voltages V
DD
≥ 4.5V.
DS70141F-page 151