DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 57

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

7.0
The data EEPROM memory is readable and writable
during normal operation over the entire V
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory as well. As described in
“Address Generator
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, is used to address the EEPROM
location being accessed. TBLRDL and TBLWTL instruc-
tions are used to read and write data EEPROM. The
dsPIC30F3010/3011 devices have 1 Kbyte (512 words)
of data EEPROM, with an address range from
0x7FFC00 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
© 2010 Microchip Technology Inc.
Note:
DATA EEPROM MEMORY
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
Units”, these registers are:
Reference
DD
Section 4.0
range. The
Manual”
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit, WR, initiates write operations, similar to
program Flash writes. This bit cannot be cleared, only
set, in software. This bit is cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register, NVMADR, remains unchanged.
7.1
A TBLRD instruction reads a word at the current
program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL [ W0 ], W4
Note:
dsPIC30F3010/3011
Reading the Data EEPROM
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
Interrupt flag bit, NVMIF in the IFS0
register, is set when the write is complete.
It must be cleared in software.
,
TBLPAG
DATA EEPROM READ
Example
; Init Pointer
; read data EEPROM
7-1.
DS70141F-page 57