DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 153

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

TABLE 20-7:
TABLE 20-8:
RCON
OSCCON 0742
OSCTUN
Legend:
Note 1:
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
2:
3:
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual “(DS70046) for descriptions of register bit fields.
Addr. Bit 15
0740 TRAPR IOPUWR BGST
0744
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual “(DS70046) for descriptions of register bit fields.
Reserved bits read as ‘1’ and must be programmed as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
—
—
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
FWDTEN
MCLREN
BKBUG
Bit 15
FCKSM<1:0>
—
—
—
Bit 14
—
—
Bit 14
COE
Bit 13
—
—
—
—
—
COSC<1:0>
—
Bit 12
Bit 13
—
—
—
—
—
—
—
Reserved
Reserved
Bit 11
—
—
—
Bit 12
(2)
(2)
—
—
—
—
—
Bit 10
—
—
—
Bit 11
—
—
—
—
—
—
—
Bit 9
NOSC<1:0>
—
—
(1)
PWMPIN
Bit 10
Bit 8
—
—
—
—
—
—
—
(1)
EXTR
Bit 7
FOS<2:0>
—
POST<1:0>
HPOL
Bit 9
—
—
—
—
Reserved
SWR
Bit 6
—
Reserved
LPOL
Bit 8
(2)
—
—
—
SWDTEN
LOCK
Bit 5
(2)
—
BOREN
Bit 7
—
—
—
—
—
—
WDTO
Bit 4
—
—
Bit 6
—
—
—
—
—
—
—
SLEEP
Bit 3
CF
Bit 5
—
FWPSA<1:0>
—
—
—
—
Bit 2
IDLE
BORV<1:0>
—
TUN<3:0>
LPOSCEN OSWEN Depends on Configuration bits.
Bit 4
—
—
—
—
Bit 1
BOR
Bit 3
—
—
—
Bit 0
POR
Reserved
FPR<4:0>
Depends on type of Reset.
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
(3)
Reset State
(2)
(2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0