DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 59

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

7.3
To write an EEPROM data location, the following
sequence must be followed:
1.
2.
3.
EXAMPLE 7-4:
© 2010 Microchip Technology Inc.
; Point to data memory
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
; Operate key to allow write operation
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Erase data EEPROM word.
a)
b)
c)
d)
e)
f)
g)
h)
Write the data word into the data EEPROM write
latches.
Program 1 data word into the data EEPROM.
a)
b)
c)
d)
e)
f)
g)
MOV
MOV
MOV
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
Writing to the Data EEPROM
Select the word, data EEPROM, erase and
set WREN bit in the NVMCON register.
Write the address of word to be erased into
the NVMADRU/NVMADR.
Enable the NVM interrupt (optional).
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Set the WR bit. This will begin the erase cycle.
Either poll the NVMIF bit or wait for the
NVMIF interrupt.
The WR bit is cleared when the erase cycle
ends.
Select the word, data EEPROM, program and
set the WREN bit in the NVMCON register.
Enable the NVM write done interrupt
(optional).
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Set the WR bit. This will begin the program
cycle.
Either poll the NVMIF bit or wait for the
NVM interrupt.
The WR bit is cleared when the write cycle
ends.
#5
DATA EEPROM WORD WRITE
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#LOW(WORD),W2
W2
#0x4004,W0
W0
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
TBLPAG
[ W0]
NVMCON
NVMKEY
NVMKEY
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution. The WREN bit should be kept clear at all
times, except when updating the EEPROM. The
WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt, or poll this bit. NVMIF
must be cleared by software.
7.3.1
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in
; Init pointer
; Get data
; Write data
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Initiate program sequence
dsPIC30F3010/3011
WRITING A WORD OF DATA
EEPROM
Example
7-4.
DS70141F-page 59