DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 88

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

dsPIC30F3010/3011
13.5
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
13.6
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
DS70141F-page 88
Output Compare Operation During
CPU Sleep Mode
Output Compare Operation During
CPU Idle Mode
13.7
The output compare channels have the ability to
generate an interrupt on a compare match for
whichever Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
register, and must be cleared in software. The interrupt
is enabled via the respective Compare Interrupt Enable
(OCxIE) bit, located in the corresponding IEC register.
For the PWM mode, when an event occurs, the respec-
tive Timer Interrupt Flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The TxIF bit
is located in the IFS0 register, and must be cleared in
software. The interrupt is enabled via the respective
Timer Interrupt Enable bit (T2IE or T3IE), located in the
IEC0 register. The output compare interrupt flag is
never set during the PWM mode of operation.
Output Compare Interrupts
© 2010 Microchip Technology Inc.