P87LPC768BD,512 NXP Semiconductors, P87LPC768BD,512 Datasheet - Page 19

• Manufacturer Part Number: P87LPC768BD,512
• Description: IC 80C51 MCU 4K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC768BD,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 10 MHz, 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3218-5; 935267360512; P87LPC768BD

Philips Semiconductors
The width of each PWM output pulse is determined by the value in
the appropriate compare shadow registers, CPSW0 through
CPSW4, CPSW0–3 for bits 0–7 and CPSW4 for bits 7 and 8. When
the counter described above reaches underflow the PWM output is
forced high. It remains high until the compare value is reached at
which point it goes low until the next underflow. The number of
microcontroller clock pulses that the PWM
by:
A compare value greater than the counter reload value results in the
PWM output being permanently high. In addition there are two
The overall functioning of the PWM module is controlled by the
contents of the PWMCON0 register. The operation of most of the
control bits is straightforward. For example there is an invert bit for
each output which causes results in the output to have the opposite
value compared to its non-inverted output. The transfer of the data
from the shadow registers to the control registers is controlled by the
PWMCON0.6 while PWMCON0.7 allows the PWM to be either in
the run or idle state. The user can monitor when underflow causes
the transfer to occur by monitoring the Transfer bit, PWCON0.6.
When the transfer takes place the PWM logic automatically resets
this bit.
The fact that the transfer from the shadow to the working registers
only occurs when there is an underflow in the counter results in the
need for the user’s program to observe the following precautions. If
2002 Mar 12
CPSW0: Compare Shadow register 0
Addr:
Reset Value:
CPSW1: Compare Shadow register 1
Addr:
Reset Value:
CPSW2: Compare Shadow register 2
Addr:
Reset Value:
CPSW3: Compare Shadow register 3
Addr:
Reset Value:
CPSW4: Compare Shadow register 4
Addr:
Reset Value:
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
t
HI
= (CNSW – CPSW
CPSW07
CPSW17
CPSW27
CPSW37
CPSW39
7
7
7
7
7
n
0D3H
00H
0D4H
00H
0D5H
00H
0D6H
00H
0D7H
00H
+1)
CPSW06
CPSW16
CPSW26
CPSW36
CPSW38
6
6
6
6
6
n
output is high is given
CPSW05
CPSW15
CPSW25
CPSW35
CPSW29
5
5
5
5
5
CPSW04
CPSW14
CPSW24
CPSW34
CPSW28
4
4
4
4
4
17
special cases. A compare value of all zeroes, 000, causes the
output to remain permanently high. A compare value of all ones,
3FF, results in the PWM output remaining permanently low. Again
the compare value is loaded into a shadow register. The transfer
from this holding register to the actual compare register is under
program control.
The register assignments are shown below where the number
immediately following “CPSW” identifies the PWM output. Thus
CPSW0 controls the width of PWM0, CPSW1 the width of PWM1
etc. In the case of two digits following “CPSW,” e.g. CPSW00, the
second digit refers to the bit of the compare value. Thus CPSW00
represents the value loaded into bit 0 of the PWM0 compare register
PWMCON1 is written with Transfer set without Run being enabled
the transfer will never take place. Thus if a subsequent write sets
Run without Transfer the compare and counter values will not be
those expected. If Transfer and Run are set, and prior to underflow
there is a subsequent load of PWMCON0 which sets Run but not
Transfer, the transfer will never take place. Again the compare and
counter values that existed prior to the update attempt will be used.
As outlined above the Transfer bit can be polled to determine when
the transfer occurs. Unless there is a compelling reason to do
otherwise, it is recommended that both Run, PWMCON0.7, and
Transfer, PWMCON0.7, be set when PWMCON0 is written.
When the Run bit, PWMCON0.7, is cleared the PWM outputs take
on the state they had just prior to the bit being cleared. In general
this state is not known. In order to place the outputs in a known
CPSW03
CPSW13
CPSW23
CPSW33
CPSW19
3
3
3
3
3
CPSW02
CPSW12
CPSW22
CPSW32
CPSW18
2
2
2
2
2
CPSW01
CPSW11
CPSW21
CPSW31
CPSW09
1
1
1
1
1
P87LPC768
Preliminary data
CPSW00
CPSW10
CPSW20
CPSW30
CPSW08
0
0
0
0
0