P87LPC768BD,512 NXP Semiconductors, P87LPC768BD,512 Datasheet - Page 39

• Manufacturer Part Number: P87LPC768BD,512
• Description: IC 80C51 MCU 4K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC768BD,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 10 MHz, 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3218-5; 935267360512; P87LPC768BD

Philips Semiconductors
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 27
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to the Timer when TRn = 1 and
either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INTn, to facilitate pulse width
2002 Mar 12
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
TCON
OSC/6
OSC/12
BIT
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
INTn PIN
Tn PIN
GATE
TRn
Address: 88h
Bit Addressable
OR
SYMBOL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1
7
FUNCTION
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
interrupt is processed, or by software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
C/T = 1
Figure 27. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
C/T = 0
TR1
Figure 26. Timer/Counter Control Register (TCON)
6
TF0
5
CONTROL
TR0
4
37
IE1
3
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 26). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See
Figure 27. There are two different GATE bits, one for Timer 1
(TMOD.7) and one for Timer 0 (TMOD.3).
(5 BITS)
TLn
IT1
2
(8 BITS)
IE0
THn
1
TOGGLE
OVERFLOW
IT0
0
TnOE
TFn
P87LPC768
Reset Value: 00h
SU01172
INTERRUPT
Preliminary data
Tn PIN
SU01173