P87LPC768BD,512 NXP Semiconductors, P87LPC768BD,512 Datasheet - Page 34

• Manufacturer Part Number: P87LPC768BD,512
• Description: IC 80C51 MCU 4K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC768BD,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 10 MHz, 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3218-5; 935267360512; P87LPC768BD

temporarily run the CPU at a lower rate, reducing power consumption,
Philips Semiconductors
CPU Clock Modification: CLKR and DIVM
For backward compatibility, the CLKR configuration bit allows
setting the P87LPC768 instruction and peripheral timing to match
standard 80C51 timing by dividing the CPU clock by two. Default
timing for the P87LPC768 is 6 CPU clocks per machine cycle while
standard 80C51 timing is 12 clocks per machine cycle. This
division also applies to peripheral timing, allowing 80C51 code that
is oscillator frequency and/or timer rate dependent. The CLKR bit
is located in the EPROM configuration register UCFG1, described
under EPROM Characteristics
In addition to this, the CPU clock may be divided down from the
oscillator rate by a programmable divider, under program control.
This function is controlled by the DIVM register. If the DIVM register
is set to zero (the default value), the CPU will be clocked by either
the unmodified oscillator rate, or that rate divided by two, as
determined by the previously described CLKR function.
When the DIVM register is set to some value N (between 1 and 255),
the CPU clock is divided by 2 * (N + 1). Clock division values from 4
through 512 are thus possible. This feature makes it possible to
in a manner similar to Idle mode. By dividing the clock, the CPU can
retain the ability to respond to events other than those that can cause
interrupts (i.e. events that allow exiting the Idle mode) by executing its
normal program at a lower rate. This can allow bypassing the
oscillator startup time in cases where Power Down mode would
otherwise be used. The value of DIVM may be changed by the
program at any time without interrupting code execution.
2002 Mar 12
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
CRYSTAL: MEDIUM FREQUENCY
CRYSTAL: HIGH FREQUENCY
CRYSTAL: LOW FREQUENCY
INTERNAL RC OSCILLATOR
EXTERNAL CLOCK INPUT
POWER MONITOR RESET
FOSC2 (UCFG1.2)
FOSC1 (UCFG1.1)
FOSC0 (UCFG1.0)
POWER DOWN
Figure 21. Block Diagram of Oscillator Control
CLOCK SELECT
CLOCK
SOURCES
SELECT
CLOCK
XTAL
OUT
32
register is set so that the cause of processor reset may be determined
Power Monitoring Functions
The P87LPC768 incorporates power monitoring functions designed
to prevent incorrect operation during initial power up and power loss
or reduction during operation. This is accomplished with two
hardware functions: Power-On Detect and Brownout Detect.
Brownout Detection
The Brownout Detect function allows preventing the processor from
failing in an unpredictable manner if the power supply voltage drops
below a certain level. The default operation is for a brownout
detection to cause a processor reset, however it may alternatively
be configured to generate an interrupt by setting the BOI bit in the
AUXR1 register (AUXR1.5).
The P87LPC768 allows selection of two Brownout levels: 2.5 V or
3.8 V. When V
detector triggers and remains active until V
above the Brownout Detect voltage. When Brownout Detect causes
a processor reset, that reset remains active as long as V
below the Brownout Detect voltage. When Brownout Detect
generates an interrupt, that interrupt occurs once as V
from above to below the Brownout Detect voltage. For the interrupt
to be processed, the interrupt system and the BOI interrupt must
both be enabled (via the EA and EBO bits in IEN0).
When Brownout Detect is activated, the BOF flag in the PCON
by software. This flag will remain set until cleared by software.
COUNT
RESET
OSCILLATOR STARTUP TIMER
10-BIT RIPPLE COUNTER
(UCFG1.3)
CLKR
DD
drops below the selected voltage, the brownout
COUNT 1024
COUNT 256
(DIVM REGISTER)
CLKR SELECT
DIVIDE-BY-M
AND
1/ 2
DD
P87LPC768
is returns to a level
Preliminary data
DD
SU01167
DD
crosses
CLOCK
remains
CPU