P87LPC768BD,512 NXP Semiconductors, P87LPC768BD,512 Datasheet - Page 20

• Manufacturer Part Number: P87LPC768BD,512
• Description: IC 80C51 MCU 4K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC768BD,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 10 MHz, 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3218-5; 935267360512; P87LPC768BD

Philips Semiconductors
state when Run is cleared the Compare registers can be written to
either the “always 1” or “always 0” so the output will have the output
desired when the counter is halted. After this PWMCON0 should be
written with the Transfer and Run bits are enabled. After this is
done PWMCON0 to is polled to find that the Transfer has taken
place. Once the transfer has occurred the Run bit in PWMCON0
can be cleared. The outputs will retain the state they had just prior
to the Run being cleared. If the Brake pin (see discussion below in
The Brake function, which is controlled by the contents of the
PWMCON1 register, is somewhat unique. In general when Brake is
asserted the four PWM outputs are forced to a user selected state,
namely the state selected by PWMCON1 bits 0 to 3.
As shown in the description of the operation of the PWMCON1
register if PWMCON1.4 is a “1” brake is asserted under the control
PWMCON1.7, BKCH, and PWMCON1.5, BPEN. As shown if both
are a “0” Brake is asserted. If PWMCON1.7 is a “1” brake is
asserted when the run bit, PWMCON0.7, is a “0.” If PWMCON1.6 is
a “1” brake is asserted when the Brake Pin, P0.2, has the same
polarity as PWMCON1.6. When brake is asserted in response to
this pin the RUN bit, PWMCON0.7, is automatically cleared. The
combination of both PWMCON1.7 and PWMCON1.5 being a “1” is
not allowed.
Since the Brake Pin being asserted will automatically clear the Run
bit, PWMCON0.7, the user program can poll this bit to determine
when the Brake Pin causes a brake to occur. The other method for
detecting a brake caused by the Brake Pin would be to tie the Brake
Pin to one of the external interrupt pins. This latter approach is
2002 Mar 12
PWMCON0: PWM Control register 0
Addr: 0DAH
Reset Value: 00H
BIT
PWMCON0.7
PWMCON0.6
PWMCON0.5
PWMCON0.4
PWMCON0.2
PWMCON0.1
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
SYMBOL
PWM3I
PWM2I
PWM1I
PWM0I
XFER
RUN
FUNCTION
0= Counter Halted & Preset Value loaded. If Brake is asserted, PWMx output will be equal to the
1= Counter run
0= Counter & Compare shadow registers are not connected to the active registers
1= Shadow register contents transferred to active registers, at the next Counter underflow This bit
0= PWM3 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’
1= PWM3 output is inverted. Output is a ‘0’ from the start of the cycle until compare; ’0’ thereafter.
0= PWM2 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’
1= PWM2 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.
0= PWM1 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’
1= PWM1 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.
0= PWM0 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’
1= PWM0 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.
RUN
value of the corresponding PWMxB bit (PWMCON1[3:0]). If Brake is not asserted, PWMx
output will be equal to the Value after compare
is auto–cleared by hardware after the data transfer from shadow to active registers
thereafter.
thereafter.
thereafter.
thereafter.
7
XFER
6
PWM3I
5
18
control the brake function, the “Brake when not running” function can
section concerning the operation of PWMCON1) is not used to
be used to cause the outputs to have a given state when the PWM
is halted. This approach should be used only in time critical
situations when there is not sufficient time to use the approach
outlined above since going from the Brake state to run without
causing an undefined state on the outputs is not straightforward. A
discussion on this topic is included in the section on PWMCON1.
needed if the Brake signal can be of insufficient length to ensure
that it can be captured by a polling routine.
When, after being asserted, the condition causing the brake is
removed, the PWM outputs go to whatever state that had
immediately prior to the brake. This means that in order to go from
brake being asserted to having the PWM run without going through
an indeterminate state care must be taken. If the Brake Pin causes
brake to be asserted the following prototype code will allow the
PWM to go from brake to run smoothly.
Rewrite PWMCON1 to change from Brake Pin enabled to S/W
Brake
Write CPSW.(0:4) to always “1”, 11 h, or always “0” 00 h, to give
brake pattern
Set PWMCON0 to enable Run and Transfer.
Poll Brake Pin until it is no longer active. When no longer active:
PWM2I
4
3
–
PWM1I
2
PWM0I
1
P87LPC768
SU01387
0
–
Preliminary data