P87LPC768BD,512 NXP Semiconductors, P87LPC768BD,512 Datasheet - Page 21

• Manufacturer Part Number: P87LPC768BD,512
• Description: IC 80C51 MCU 4K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC768BD,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 10 MHz, 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3218-5; 935267360512; P87LPC768BD

Philips Semiconductors
2002 Mar 12
Poll PWMCON0 to find that Transfer Bit PWMCON0.6 is “0”.
When “0”:
Write CNSW.(0:1) and CPSW.(0:4) for desired pulse widths and
counter reload values
Set PWMCON0 to Run and Transfer
PWMCON1: PWM Control register 1
Addr: 0DBH
Reset Value: 00H
BIT
PWMCON1.7
PWMCON1.6
PWMCON1.5
PWMCON1.4
PWMCON1.3
PWMCON1.2
PWMCON1.1
PWMCON1.0
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
BPEN
0
0
1
1
SYMBOL
PWM3B
PWM2B
PWM1B
PWM0B
BKCH
BPEN
BKEN
BKPS
BKCH
0
1
0
1
Always On, (Software Brake)
On when PWM not running (Brake Pin has no effect)
On when Brake Pin asserted (PWM run has no effect)
Not Allowed
FUNCTION
See table below
0= ”Brake” is asserted if P0.2(Brake Pin) is low.
1= ”Brake” is asserted if P0.2(Brake Pin) is high.
See table below.
0= ”Brake” is never asserted.
1= ”Brake” is enabled per table below.
0= PWM3 is low, when Brake is asserted.
1= PWM3 is high, when Brake is asserted.
0= PWM2 is low, when Brake is asserted.
1= PWM2 is high, when Brake is asserted.
0= PWM1 is low, when Brake is asserted.
1= PWM1 is high, when Brake is asserted.
0= PWM0 is low, when Brake is asserted.
1= PWM0 is high, when Brake is asserted.
BKCH
7
BKPS
6
BRAKE CONDITION
BPEN
5
19
Note that if a narrow pulse on the Brake Pin causes brake to be
asserted, it may not be possible to go through the above code
before the end of the pulse. In this case, in addition to the code
shown, an external latch on the Brake Pin may be required to
ensure that there is a smooth transition in going from brake to run.
The details for PWMCON1 are shown in the following table.
BKEN
4
PWM3B
3
PWM2B
2
PWM1B
1
P87LPC768
PWM0B
SU01388
0
Preliminary data