MCU ARM 64KB FLASH/TIMER 100LQFP

STM32F101V8T6

Manufacturer Part NumberSTM32F101V8T6
DescriptionMCU ARM 64KB FLASH/TIMER 100LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101V8T6 datasheet
 


Specifications of STM32F101V8T6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o80
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size10K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-LQFP
Processor SeriesSTM32F101xCoreARM Cortex M3
Data Bus Width32 bitData Ram Size10 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os100Number Of Timers3 x 16 bit
Operating Supply Voltage2 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 16 Channel
For Use With497-10030 - STARTER KIT FOR STM32497-8853 - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-8304 - KIT STM32 MOTOR DRIVER BLDC497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCULead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Other names497-6060
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Page 16/87

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Description
2.3.6
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9
Power supply schemes
V
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
DD
Provided externally through V
V
, V
SSA
DDA
and PLL (minimum voltage to be applied to V
V
and V
DDA
SSA
V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V
For more details on how to connect power pins, refer to
2.3.10
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
/V
power supply and compares it to the V
DD
DDA
generated when V
16/87
Figure 2
for details on the clock tree.
pins.
DD
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
must be connected to V
DD
DD
is below a specified threshold, V
DD
/V
drops below the V
DD
DDA
PVD
Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB
is 2.4 V when the ADC is used).
DDA
and V
, respectively.
SS
is not present.
Figure 11: Power supply
, without the need for an
POR/PDR
threshold. An interrupt can be
PVD
threshold and/or when V
/V
DD
scheme.
is higher
DDA