STM32F101V8T6 STMicroelectronics, STM32F101V8T6 Datasheet - Page 59

MCU ARM 64KB FLASH/TIMER 100LQFP

STM32F101V8T6

Manufacturer Part Number
STM32F101V8T6
Description
MCU ARM 64KB FLASH/TIMER 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101V8T6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
10 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
100
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-6060
STM32F101x8, STM32F101xB
Figure 27. I/O AC characteristics definition
EXT ERNAL
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) ≤ 2/3)T and if the duty cycle is (45-55%)
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
(see
PU
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table
8.
Table 37.
NRST pin characteristics
Symbol
(1)
V
NRST Input low level voltage
IL(NRST)
(1)
V
NRST Input high level voltage
IH(NRST)
NRST Schmitt trigger voltage
V
hys(NRST)
hysteresis
R
Weak pull-up equivalent resistor
PU
(1)
V
NRST Input filtered pulse
F(NRST)
(1)
V
NRST Input not filtered pulse
NF(NRST)
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
the series resistance must be minimum
Figure 28. Recommended NRST pin protection
External
reset circuit
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table
37. Otherwise the reset will not be taken into account by the device.
90%
50%
10%
t r(I O)out
when loaded by 50pF
Table
34).
Parameter
Conditions
(2)
V
.
(~10% order)
V DD
(1)
R PU
(2)
NRST
0.1 µF
Doc ID 13586 Rev 14
Electrical characteristics
10%
50%
90%
t r(I O)out
T
Table 37
are derived from tests
supply voltage conditions summarized
DD
Min
Typ
Max
–0.5
2
V
DD
200
=
V
30
40
IN
SS
300
Internal reset
Filter
STM32F10x
ai14132d
max level specified in
IL(NRST)
ai14131
Unit
0.8
V
+0.5
mV
50
100
ns
ns
to
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