MCU ARM 64KB FLASH/TIMER 100LQFP

STM32F101V8T6

Manufacturer Part NumberSTM32F101V8T6
DescriptionMCU ARM 64KB FLASH/TIMER 100LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101V8T6 datasheet
 


Specifications of STM32F101V8T6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o80
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size10K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-LQFP
Processor SeriesSTM32F101xCoreARM Cortex M3
Data Bus Width32 bitData Ram Size10 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os100Number Of Timers3 x 16 bit
Operating Supply Voltage2 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 16 Channel
For Use With497-10030 - STARTER KIT FOR STM32497-8853 - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-8304 - KIT STM32 MOTOR DRIVER BLDC497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCULead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Other names497-6060
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Page 61/87

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STM32F101x8, STM32F101xB
2
Table 39.
I
C characteristics
Symbol
t
SCL clock low time
w(SCLL)
t
SCL clock high time
w(SCLH)
t
SDA setup time
su(SDA)
t
SDA data hold time
h(SDA)
t
r(SDA)
SDA and SCL rise time
t
r(SCL)
t
f(SDA)
SDA and SCL fall time
t
f(SCL)
t
Start condition hold time
h(STA)
Repeated Start condition setup
t
su(STA)
time
t
Stop condition setup time
su(STO)
Stop to Start condition time (bus
t
w(STO:STA)
free)
C
Capacitive load for each bus line
b
1. Guaranteed by design, not tested in production.
2. f
must be higher than 2 MHz to achieve standard mode I
PCLK1
4 MHz to achieve fast mode I
maximum I2C fast mode clock.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Standard mode I
Parameter
Min
4.7
4.0
250
(3)
0
4.0
4.7
4.0
4.7
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
Doc ID 13586 Rev 14
Electrical characteristics
2
(1)
2
(1)(2)
C
Fast mode I
C
Max
Min
Max
1.3
0.6
100
(4)
(3)
0
900
1000
20+0.1C
300
b
300
300
0.6
0.6
0.6
1.3
400
400
2
C frequencies. It must be higher than
Unit
µs
ns
µs
µs
µs
pF
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