STM32F101V8T6 STMicroelectronics, STM32F101V8T6 Datasheet - Page 17
Manufacturer Part Number
MCU ARM 64KB FLASH/TIMER 100LQFP
Specifications of STM32F101V8T6
I²C, IrDA, LIN, SPI, UART/USART
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
Program Memory Size
64KB (64K x 8)
Program Memory Type
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
-40°C ~ 85°C
Package / Case
ARM Cortex M3
Data Bus Width
Data Ram Size
I2C, SPI, USART
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
12 bit, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
than the V
threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Table 10: Embedded reset and power control block characteristics
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
The STM32F101xx medium-density access line supports three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Doc ID 13586 Rev 14
for the values of