EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 113

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
UART Interrupts
9-bit data, the host processor programs the parity bit generator so that it marks the byte as
either address (mark parity) or data (space parity).
UART Receiver
The receiver block controls the data reception from the RxD signal. The receiver block
implements a receiver shift register, receiver line error condition monitoring logic and
Receiver Data Ready logic. It also implements the parity checker.
The UARTx_RBR is a Read Only register of the module. The processor reads received
data from this register. The condition of the UARTx_RBR register is monitored by the DR
bit (bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is received and
transferred to the UARTx_RBR register from the receiver shift register. The DR bit is
reset only when the processor reads all of the received data bytes. If the number of bits
received is less than eight, the unused MSbs of the data byte Read are 0
For 9-bit data, the receiver checks incoming bytes for space parity. This check routine gen-
erates a line status interrupt when an address byte is received, because address bytes con-
tain mark parity bits. The processor clears the interrupt, determines if the address matches
its own, then configures the receiver to either accept the subsequent data bytes if the
address matches, or ignore the data if it does not.
The receiver uses the clock from the BRG for receiving the data. This clock must be 16
times the appropriate baud rate. The receiver synchronizes the shift clock on the falling
edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt
can be generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP mode for self-diagnostics.
There are six different sources of interrupts from the UART.
The six sources of interrupts are:
•
•
•
Transmitter (two different interrupts)
Receiver (three different interrupts)
Modem status
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F92/eZ80F93
106