EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 53

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 12. Vectored Interrupt Operation
PS015313-0508
Memory
Mode
Z80
ADL Mode
®
Mode 0
ADL
Bit
1
stored at {MBASE[7:0], I[7:0],
byte is stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit inter-
rupt vector for the highest-priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80F92 device and is therefore
not visible externally.
The response time of the CPU to an interrupt request is a function of the current instruc-
tion being executed as well as the number of wait states being asserted. The interrupt vec-
tor, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0], when the interrupt
service routine begins. The response of the CPU to a vectored interrupt on the eZ80F92
device is listed in
service routine starts. It is recommended that the Interrupt Page Address Register (I) value
be changed by the user from its default value of
between the nonmaskable interrupt vector, the RST instruction addresses, and the
maskable interrupt vectors.
MADL
Bit
0
0
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack
The ADL mode bit remains cleared to 0
The interrupt vector address is located at {MBASE, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is effectively {MBASE, PC[15:0]}
The interrupt service routine must end with RETI
IEF1
IEF2
The Starting Program Counter is PC[23:0]
Push the 3-byte return address, PC[23:0], onto the SPL stack
The ADL mode bit remains set to 1
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is {00h, PC[15:0]}
The interrupt service routine must end with RETI
Table
←
←
←
←
12. Interrupt sources are required to be active until the interrupt
0
0
0
0
←
←
({MBASE, I[7:0], IVECT[7:0]})
({00h, I[7:0], IVECT[7:0]})
1Eh
} and {MBASE, I[7:0],
00h
as this address can create conflicts
1Fh
}. The least-significant
Product Specification
eZ80F92/eZ80F93
Interrupt Controller
46