EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 58

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
WAIT States
WAIT Input Signal
Caution:
If all of the foregoing conditions are met to generate an I/O Chip Select, then the following
actions occur:
•
•
•
For each of the Chip Selects, programmable WAIT states can be asserted to provide exter-
nal devices with additional clock cycles to complete their Read or Write operations.
The number of WAIT states for a particular Chip Select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to pro-
vide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the speci-
fied number of system clock cycles.
Similar to the programmable WAIT states, an external peripheral can drive the WAIT
input pin to force the CPU to provide additional clock cycles to complete its Read or Write
operation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the
first rising edge of the internal system clock following deassertion of the WAIT pin.
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low)
IORQ is asserted (driven Low)
Depending upon the instruction, either RD or WR is asserted (driven Low)
If the WAIT pin is to be driven by an external device, the corresponding Chip
Select for the device must be programmed to provide at least one WAIT state.
Due to input sampling of the WAIT input pin (displayed in
grammable WAIT state is required to allow the external peripheral sufficient
time to assert the WAIT pin. It is recommended that the corresponding Chip Se-
lect for the external device be programmed to provide the maximum number of
WAIT states (seven).
Figure 7.Wait Input Sampling Block Diagram
Wait
Pin
System Clock
D
Q
eZ80
CPU
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
Figure
7), one pro-
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