EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 81

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Watchdog Timer Registers
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the CPU to
determine the source of the NMI event.
Watchdog Timer Control Register
The Watchdog Timer Control register, listed in
used to enable the Watchdog Timer, set the time-out period, indicate the source of the most
recent RESET, and select the required operation upon WDT time-out.
Table 27. Watchdog Timer Control Register; (WDT_CTL = 0093h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG*
[4:3]
WDT_CLK
2
Note: *RST_FLAG is only cleared by a non-WDT RESET.
Value Description
0
1
0
1
0
1
00
01
10
11
0
R/W
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a
WDT time-out resets the CPU.
WDT time-out generates a nonmaskable interrupt (NMI) to the
CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 kHz on-chip
oscillator or 50/60 Hz input as set by RTC_CTRL[4]).
Reserved.
Reserved.
Reserved.
7
0
R/W
RESET
6
0
0/1
.
R
5
Table
R/W
4
0
27, is an 8-bit Read/Write register
R/W
3
0
Product Specification
R
2
0
eZ80F92/eZ80F93
Watchdog Timer
R/W
1
0
R/W
0
0
74