EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 202

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
eZ80 Core
Interface
System Clock
WAIT
IRQ
Programming Flash Memory
Caution:
ADDR
D
Flash memory is programmed using standard I/O or memory Write operations which the
Flash memory controller automatically translates to the detailed timing and protocol
required for Flash memory. The more efficient multibyte (row) programming mode is only
available through I/O Writes.
1. The cumulative programming time subsequent to the most recent Erase cannot
2. The same byte cannot be programmed more than twice subsequent to the most
Single-Byte I/O Write Operations
A single-byte I/O Write operation uses I/O registers for setting the column, page, and row
address to be programmed. The FLASH_DATA register stores the data to be written.
While the CPU executes an output to I/O instruction to load the data into the
FLASH_DATA register, the Flash controller asserts the internal WAIT signal to stall the
CPU until the Flash Write operation is complete. A single-byte Write takes between 66 µs
and 85 µs to complete. Programming an entire row (128 bytes) using single-byte Writes
OUT
exceed 16 ms for any given row.
recent Erase.
Figure 50
17
8
Registers
To ensure data integrity and device reliability, following two main restrictions
exist when programming Flash memory:
8-bit downcounter
Control
Flash
Clock Divider
Figure 50. Flash Memory Block Diagram
displays a simplified block diagram of the Flash controller.
Machine
Flash
State
7
FADDR
FCNTL
MAIN_INFO
FD
CPUD
IN
ADDR GEN
OUT
17
8
9
8
Product Specification
512 bytes
256 KB
eZ80F92/eZ80F93
Flash
+
Flash Memory
FD
OUT
8
195