EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 144

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Table 74. SPI Control Register(SPI_CTL = 00BAh)
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See
Table 75. SPI Status Register(SPI_SR = 00BBh)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
3
CPOL
2
CPHA
[1:0]
Bit
Reset
CPU Access
Note: R = Read Only.
Table
75.
Value Description
0
1
0
0
1
0
1
0
1
0
1
00
R/W
SPI system interrupt is disabled.
SPI system interrupt is enabled.
Reserved.
SPI is disabled.
SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
Master SCK pin idles in a Low (0) state.
Master SCK pin idles in a High (1) state.
SS must go High after transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
Reserved.
R
7
0
7
0
R
R
6
0
6
0
R/W
R
5
0
5
0
R/W
R
4
0
4
0
R/W
R
3
0
3
0
Product Specification
Serial Peripheral Interface
R/W
R
2
1
2
0
eZ80F92/eZ80F93
R
R
1
0
1
0
R
R
0
0
0
0
137