EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 148

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

I2C Serial I/O Interface
PS015313-0508
I
2
C General Characteristics
The I
modes:
1. MASTER TRANSMIT
2. MASTER RECEIVE
3. SLAVE TRANSMIT
4. SLAVE RECEIVE
The I
and SCL are bidirectional lines, connected to a positive supply voltage via an external
pull-up resistor. When the bus is free, both lines are High. The output stages of devices
connected to the bus must be configured as open-drain outputs. Data on the I
transferred at a rate of up to 100 kbps in STANDARD mode, or up to 400 kbps in FAST
mode. One clock pulse is generated for each data bit transferred.
Clocking Overview
If another device on the I
the I
mined by the device that generates the shortest High clock period. The Low period of the
clock is determined by the device that generates the longest Low clock period.
A slave may stretch the Low period of the clock to slow down the bus master. The Low
period may also be stretched for handshaking purposes. This can be done after each bit
transfer or each byte transfer. The I
IFLG bit in the I2C_CTL register is cleared.
Bus Arbitration Overview
In MASTER mode, the I
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge
bit, the I
address, the I
the general call address.
2
2
2
C synchronizes its clock to the I
C interface consists of the Serial Clock (SCL) and the Serial Data (SDA). Both SDA
C serial I/O bus is a two-wire communication interface that can operate in four
2
C returns to the idle state. If arbitration is lost during the transmission of an
2
C switches to SLAVE mode so that it can recognize its own slave address or
2
2
C checks that each transmitted logic 1 appears on the I
C bus drives the clock line when the I
2
C stretches the clock after each byte transfer until the
2
C bus clock. The High period of the clock is deter-
2
Product Specification
C is in MASTER mode,
I2C Serial I/O Interface
2
C bus can be
2
C bus as
141