EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 39

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Reset
PS015313-0508
Reset Operation
Power-On Reset
Note:
The Reset controller within the eZ80F92 device provides a consistent reset function for all
types of resets that can affect the system. A system reset, referred in this document as
RESET, returns the eZ80F92 device to a defined state. All internal registers affected by
RESET return to their default conditions. RESET configures the GPIO port pins as inputs
and clears the CPU’s Program Counter to
during RESET.
The events that can cause a RESET are:
•
•
•
•
•
•
During a RESET, an internal RESET mode timer holds the system in RESET mode for
257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of all RESET events.
A Power-On Reset (POR) occurs each time the supply voltage to the part rises from below
the Voltage Brownout threshold to above the POR voltage threshold (V
bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con-
troller until the supply voltage (V
above V
Reset controller (T
until the RESET mode timer expires. POR operation is displayed in
The signals in this figure are not drawn to scale and are for displaying purposes only.
Power-On Reset (POR)
Low-Voltage Brownout (VBO)
External RESET pin assertion
Watchdog Timer (WDT) time-out when configured to generate a RESET
Real-Time Clock alarm with the CPU in low-power SLEEP mode
Execution of a debug reset command
You must determine if 257 SCLK cycles provides sufficient time for the primary
crystal oscillator to stabilize.
POR
, an on-chip analog delay element briefly maintains the RESET signal to the
ANA
). After this analog delay, the eZ80F92 device is in RESET mode
CC
) exceeds the POR voltage threshold. After V
000000h
. Program code execution ceases
Product Specification
Figure 3
POR
). The internal
on page 33.
CC
Reset
rises
32