EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 171

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
ZDI Clock and Data Conventions
ZDI START Condition
The two pins used for communication with the ZDI block are the ZDI Clock pin (ZCL)
and the ZDI Data pin (ZDA). On the eZ80F92 device, the ZCL pin is shared with the TCK
pin while the ZDA pin is shared with the TDI pin. The ZCL and ZDA pin functions are
only available when the On-Chip Instrumentation is disabled and the ZDI is therefore
enabled. For general data communication, the data value on the ZDA pin can change only
when ZCL is Low (0). The only exception is the ZDI START bit, which is indicated by a
High-to-Low transition (falling edge) on the ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the msb (bit 7) of each byte being first in time,
and the lsb (bit 0) last in time. All information is passed between the master and the slave
in 8-bit (single-byte) units. Each byte is transferred with nine clock cycles: eight to shift
the data, and ninth for internal operations.
All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low tran-
sition of ZDA when ZCL is High. The ZDI slave on the eZ80F92 device continually mon-
itors the ZDA and ZCL lines for the START signal and does not respond to any command
until this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the
beginning of a data transfer with the ZDI block.
play a valid ZDI START signal prior to writing and reading data, respectively. A Low-to-
High transition of ZDA while the ZCL is High yields no effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as displayed
in
ZCL as displayed in
stops during the ninth cycle and holds the ZCL signal High.
ZDA
ZCL
Figure
39. Data is shifted out during a Read from the ZDI block on the falling edge of
Start Signal
Figure 40
ZDI Data In
(Write)
Figure 39.ZDI Write Timing
on page 165. When an operation is completed, the master
ZDI Data In
Figure 39
(Write)
and
Figure 40
Product Specification
eZ80F92/eZ80F93
Zilog Debug Interface
on page 165 dis-
164