R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 16

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.6
9.7
9.8
9.9
Rev. 2.00 Sep. 24, 2008 Page xiv of xxxii
9.5.3
9.5.4
9.5.5
9.5.6
Basic Bus Interface ........................................................................................................... 244
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
9.6.7
Byte Control SRAM Interface .......................................................................................... 257
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
9.7.8
Burst ROM Interface ........................................................................................................ 265
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
Address/Data Multiplexed I/O Interface........................................................................... 270
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
9.9.10
Chip Select Signals ........................................................................................... 230
External Bus Interface ...................................................................................... 231
Area and External Bus Interface ....................................................................... 236
Endian and Data Alignment.............................................................................. 241
Data Bus ........................................................................................................... 244
I/O Pins Used for Basic Bus Interface .............................................................. 244
Basic Timing..................................................................................................... 245
Wait Control ..................................................................................................... 251
Read Strobe (RD) Timing................................................................................. 253
Extension of Chip Select (CS) Assertion Period............................................... 254
DACK and EDACK Signal Output Timing...................................................... 256
Byte Control SRAM Space Setting................................................................... 257
Data Bus ........................................................................................................... 257
I/O Pins Used for Byte Control SRAM Interface ............................................. 258
Basic Timing..................................................................................................... 259
Wait Control ..................................................................................................... 261
Read Strobe (RD) ............................................................................................. 263
Extension of Chip Select (CS) Assertion Period............................................... 263
DACK and EDACK Signal Output Timing...................................................... 263
Burst ROM Space Setting................................................................................. 265
Data Bus ........................................................................................................... 265
I/O Pins Used for Burst ROM Interface............................................................ 266
Basic Timing..................................................................................................... 267
Wait Control ..................................................................................................... 269
Read Strobe (RD) Timing................................................................................. 269
Extension of Chip Select (CS) Assertion Period............................................... 269
Address/Data Multiplexed I/O Space Setting ................................................... 270
Address/Data Multiplex.................................................................................... 270
Data Bus ........................................................................................................... 270
I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 271
Basic Timing..................................................................................................... 272
Address Cycle Control...................................................................................... 274
Wait Control ..................................................................................................... 275
Read Strobe (RD) Timing................................................................................. 275
Extension of Chip Select (CS) Assertion Period............................................... 277
DACK and EDACK Signal Output Timing...................................................... 279