R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 301

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.8.4
The number of access cycles in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits
CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by
the CPU or EXDMAC cluster transfer, the settings in RDNCR and bits CSXTn in CSACR (n = 0
to 7) are ignored.
From one to eight cycles can be selected for the burst cycle, according to the settings of bits
BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In
addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed
according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR.
The basic access timing for burst ROM space is shown in figures 9.29 and 9.30.
Upper
Lower
address bus
CSn
AS
RD
Data bus
BS
RD/WR
address bus
Figure 9.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)
Note: n = 1, 0
Basic Timing
T
1
Full access
T
2
T
3
T
1
Rev. 2.00 Sep. 24, 2008 Page 267 of 1468
T
Burst access
2
Section 9 Bus Controller (BSC)
T
1
REJ09B0412-0200
T
2

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