R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 573

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
Figure 11.63 shows an example of cluster transfer mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. At the end of the last cluster write cycle, acceptance
resumes and EDREQ pin low level sampling is performed again. This sequence of operations is
repeated until the end of the transfer.
When NRD bit = 0 in EDMDR, acceptance resumes at the end of the last cluster write cycle and
EDREQ pin low level sampling is performed again. This sequence of operations is repeated until
the end of the transfer.
When NRD bit = 1 in EDMDR, acceptance resumes after one cycle from the end of the last cluster
write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations
is repeated until the end of the transfer.
Bφ
EDREQ
Address bus
EXDMA control
Channel
[1]
[2] [5]
[3] [6]
[4] [7]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
Request is cleared at the end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle stars.
Acceptance is resumed after completion of wite cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Low Level Activation Timing
Figure 11.63 Example of Cluster Transfer Mode Transfer Activated
[1]
Minimum 3 cycles
Request
Bus release
[2]
Consecutive read
[3]
Transfer source
Request clearance period
by EDREQ Pin Low Level
One cluster transfer
Consecutive write
Transfer destination
[4]
Request
Minimum 3 cycles
Bus release
[5]
Rev. 2.00 Sep. 24, 2008 Page 539 of 1468
Section 11 EXDMA Controller (EXDMAC)
Consecutive read
[6]
Transfer source
Request clearance period
One cluster transfer
Consecutive write
REJ09B0412-0200
Transfer destination
[7]