R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 468

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
(4)
Figure 10.29 shows an example of normal transfer mode activated by the DREQ signal falling
edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the DMA write cycle,
receiving the next transfer request resumes and then a low level of the DREQ signal is detected.
This operation is repeated until the transfer is completed.
Rev. 2.00 Sep. 24, 2008 Page 434 of 1468
REJ09B0412-0200
Bφ
DREQ
Address bus
DMA
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
[4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle.
Activation Timing by DREQ Falling Edge
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
DREQ signal.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 10.29 Example of Transfer in Normal Transfer Mode Activated
Wait
[1]
Request
Bus released
Min. of 3 cycles
[2]
Read
[3]
Duration of transfer
Transfer source Transfer destination
request disabled
DMA read
cycle
Write
by DREQ Falling Edge
Transfer request enable resumed
DMA write
cycle
Wait
[4]
Request
Min. of 3 cycles
Bus released
[5]
Read
Duration of transfer
[6]
request disabled
Transfer source
DMA read
cycle
Write
Transfer request enable resumed
Transfer destination
DMA write
cycle
Wait
[7]
Bus released