R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 436

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
10.5
10.5.1
(1)
In dual address mode, the transfer source address is specified in DSAR and the transfer destination
address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data
bus width is less than the data access size or the access address is not aligned with the boundary of
the data access size, the number of bus cycles are needed more than two because one bus cycle is
divided into multiple bus cycles).
In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data
is written to the transfer destination address.
The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters,
refresh cycle, and external bus release cycle) are not generated between read and write cycles.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle. The DACK signal is not output.
Figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the
operation in dual address mode.
Rev. 2.00 Sep. 24, 2008 Page 402 of 1468
REJ09B0412-0200
Dual Address Mode
Operations
Address Modes
Figure 10.2 Example of Signal Timing in Dual Address Mode
Bφ
Address bus
RD
WR
TEND
DMA read
cycle
DSAR
DMA write
DDAR
cycle