DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 137

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.0
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33F peripherals that can utilize DMA are
listed in Table 7-1 along with their associated Interrupt
Request (IRQ) numbers.
TABLE 7-1:
© 2007 Microchip Technology Inc.
INT0
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
Timer3
SPI1
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
DCI
ECAN1 Reception
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
Note:
intervention.
DIRECT MEMORY ACCESS
(DMA)
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Peripheral
PERIPHERALS WITH DMA
SUPPORT
The
DMA
IRQ Number
controller
10
33
12
30
31
13
21
60
34
70
55
71
11
0
1
5
2
6
7
8
can
Preliminary
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
• Indirect Addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some periph-
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers
• Each channel can select from 20 possible
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
RAM to peripheral.
without automatic post-increment.
erals, the DMA RAM read/write addresses may
be partially derived from the peripheral.
transfer after one block transfer.
RAM buffer start address after every block
transfer is complete.
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
sources of data sources or destinations.
dsPIC33F
DS70165E-page 135