DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 362

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

dsPIC33F
DCI I/O Pins ...................................................................... 261
DCI Module
Development Support ....................................................... 305
DMA
DMA Module
DMAC Operating Modes ................................................... 136
DMAC Registers ............................................................... 136
DSP Engine......................................................................... 33
E
ECAN Module
Electrical Characteristics................................................... 309
Enhanced CAN Module..................................................... 231
Equations
DS70165E-page 360
Receive Status Bits ................................................... 267
Sample Clock Edge Control Bit................................. 266
Slave Frame Sync Operation .................................... 264
Slot Enable Bits Operation with Frame Sync ............ 266
Slot Status Bits.......................................................... 268
Synchronous Data Transfers .................................... 266
Transmit Slot Enable Bits.......................................... 266
Transmit Status Bits .................................................. 267
Transmit/Receive Shift Register ............................... 261
Underflow Mode Control Bit ...................................... 268
Word Size Selection Bits........................................... 263
COFS ........................................................................ 261
CSCK ........................................................................ 261
CSDI ......................................................................... 261
CSDO........................................................................ 261
Register Map............................................................... 64
Interrupts and Traps.................................................. 138
Request Source Selection ........................................ 138
DMA Register Map...................................................... 56
Addressing ................................................................ 137
Byte or Word Transfer............................................... 137
Continuous or One-Shot ........................................... 138
Manual Transfer ........................................................ 138
Null Data Peripheral Write ........................................ 137
Ping-Pong ................................................................. 138
Transfer Direction ..................................................... 137
DMAxCNT ................................................................. 136
DMAxCON ................................................................ 136
DMAxPAD ................................................................. 136
DMAxREQ ................................................................ 136
DMAxSTA ................................................................. 136
DMAxSTB ................................................................. 136
Multiplier...................................................................... 35
Baud Rate Setting..................................................... 236
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 58
ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 58
ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 59
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 61
ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 61, 62
Frame Types ............................................................. 231
Message Reception .................................................. 233
Message Transmission ............................................. 235
Modes of Operation .................................................. 233
Overview ................................................................... 231
AC ............................................................................. 316
A/D Conversion Clock Period ................................... 278
Bit Clock Frequency .................................................. 265
Calculating the PWM Period ..................................... 172
Calculation for Maximum PWM Resolution............... 172
COFSG Period .......................................................... 263
Device Operating Frequency .................................... 150
PWM Period .............................................................. 178
Preliminary
Errata .................................................................................. 21
F
Flash Program Memory ...................................................... 77
Flexible Configuration ....................................................... 289
FSCM
I
I/O Ports............................................................................ 159
I
I
I
In-Circuit Debugger........................................................... 295
In-Circuit Emulation .......................................................... 289
In-Circuit Serial Programming (ICSP)....................... 289, 295
Infrared Support
Input Capture
Input Change Notification Module..................................... 160
Instruction Addressing Modes ............................................ 67
Instruction Set
2
2
2
C
C Module
S Mode Operation .......................................................... 269
PWM Resolution ....................................................... 178
Relationship Between Device and SPI
Serial Clock Rate ...................................................... 213
Time Quantum for Clock Generation ........................ 237
UART Baud Rate with BRGH = 0 ............................. 224
UART Baud Rate with BRGH = 1 ............................. 224
Control Registers ........................................................ 78
Operations .................................................................. 78
Programming Algorithm .............................................. 80
RTSP Operation ......................................................... 78
Table Instructions ....................................................... 77
Delay for Crystal and PLL Clock Sources................... 86
Device Resets............................................................. 86
Parallel I/O (PIO) ...................................................... 159
Write/Read Timing .................................................... 160
Addresses................................................................. 215
Baud Rate Generator ............................................... 213
General Call Address Support .................................. 215
Interrupts .................................................................. 213
IPMI Support............................................................. 215
Master Mode Operation
Operating Modes ...................................................... 213
Registers .................................................................. 213
Slave Address Masking ............................................ 215
Slope Control ............................................................ 216
Software Controlled Clock Stretching
I2C1 Register Map...................................................... 53
I2C2 Register Map...................................................... 53
Data Justification ...................................................... 269
Frame and Data Word Length Selection .................. 269
Built-in IrDA Encoder and Decoder........................... 225
External IrDA, IrDA Clock Output ............................. 225
Registers .................................................................. 170
File Register Instructions ............................................ 67
Fundamental Modes Supported ................................. 68
MAC Instructions ........................................................ 68
MCU Instructions ........................................................ 67
Move and Accumulator Instructions............................ 68
Other Instructions ....................................................... 68
Overview................................................................... 300
Summary .................................................................. 297
Clock Speed ..................................................... 208
Clock Arbitration ............................................... 216
Multi-Master Communication, Bus
(STREN = 1) ..................................................... 215
Collision and Bus Arbitration .................... 216
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