DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 200

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

dsPIC33F
16.1
A typical incremental (a.k.a. optical) encoder has three
outputs: Phase A, Phase B and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
The two channels, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction (of
the motor) is deemed negative or reverse.
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
16.2
The 16-bit up/down counter counts up or down on
every count pulse, which is generated by the difference
of the Phase A and Phase B input signals. The counter
acts as an integrator whose count value is proportional
to position. The direction of the count is determined by
the UPDN signal which is generated by the Quadrature
Encoder Interface logic.
16.2.1
Position counter error checking in the QEI is provided
for and indicated by the CNTERR bit (QEICON<15>).
The error checking only applies when the position
counter is configured for Reset on the Index Pulse
modes (QEIM<2:0> = 110 or 100). In these modes, the
contents of the POSCNT register are compared with
the values (0xFFFF or MAXCNT + 1, depending on
direction). If these values are detected, an error condi-
tion is generated by setting the CNTERR bit and a QEI
counter error interrupt is generated. The QEI counter
error interrupt can be disabled by setting the CEID bit
(DFLTCON<8>). The position counter continues to
count encoder edges after an error has been detected.
The POSCNT register continues to count up/down until
a natural rollover/underflow. No interrupt is generated
for the natural rollover/underflow event. The CNTERR
bit is a read/write bit and is reset in software by the
user.
16.2.2
The Position Counter Reset Enable bit, POSRES
(QEI<2>), controls whether the position counter is reset
when the index pulse is detected. This bit is only
applicable when QEIM<2:0> = 100 or 110.
DS70165E-page 198
Quadrature Encoder Interface
Logic
16-bit Up/Down Position
Counter Mode
POSITION COUNTER ERROR
CHECKING
POSITION COUNTER RESET
Preliminary
If the POSRES bit is set to ‘1’, then the position counter
is reset when the index pulse is detected. If the
POSRES bit is set to ‘0’, then the position counter is not
reset when the index pulse is detected. The position
counter will continue counting up or down, and will be
reset on the rollover or underflow condition.
The interrupt is still generated on the detection of the
index pulse and not on the position counter overflow/
underflow.
16.2.3
As mentioned in the previous section, the QEI logic
generates a UPDN signal, based upon the relationship
between Phase A and Phase B. In addition to the out-
put pin, the state of this internal UPDN signal is
supplied to an SFR bit, UPDN (QEICON<11>), as a
read-only bit. To place the state of this signal on an I/O
pin, the SFR bit, PCDOUT (QEICON<6>), must be set
to ‘1’.
16.3
There are two measurement modes which are
supported and are termed x2 and x4. These modes are
selected by the QEIM<2:0> mode select bits located in
SFR QEICON<10:8>.
When control bits, QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be incre-
mented or decremented. The Phase B signal is still
utilized for the determination of the counter direction,
just as in the x4 Measurement mode.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
1.
2.
When control bits, QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input sig-
nals. Every edge of both signals causes the position
counter to increment or decrement.
Within the x4 Measurement mode, there are two
variations of how the position counter is reset:
1.
2.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
Position counter reset by detection of index
pulse, QEIM<2:0> = 100.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 101.
Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 111.
Position Measurement Mode
COUNT DIRECTION STATUS
© 2007 Microchip Technology Inc.