DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 173

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.0
14.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. To initiate another single pulse output, change the
© 2007 Microchip Technology Inc.
Note:
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in steps 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
Set Timer Period register, PRy, to value equal to
or greater than value in OCxRS, the Output
Compare Secondary register.
Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the incrementing timer, TMRy, matches
the
OCxRS, the second and trailing edge (high-to-
low) of the pulse is driven onto the OCx pin. No
additional pulses are driven onto the OCx pin
and it remains at low. As a result of the second
compare match event, the OCxIF interrupt flag
bit is set, which will result in an interrupt if it is
enabled, by setting the OCxIE bit. For further
information on peripheral interrupts, refer to
Section 6.0 “Interrupt Controller”.
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer, and clear-
ing the TMRy register, are not required but may
be advantageous for defining a pulse from a
known event time boundary.
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
Output Compare
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Secondary register,
Preliminary
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. As a result of the second compare match event,
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a continu-
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse,
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in step 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
Set Timer Period register, PRy, to a value equal to
or greater than value in OCxRS, the Output
Compare Secondary register.
Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
Enable the compare time base by setting the TON
(TyCON<15>) bit to ‘1’.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the compare time base, TMRy, matches
the Output Compare Secondary register, OCxRS,
the second and trailing edge (high-to-low) of the
pulse is driven onto the OCx pin.
the OCxIF interrupt flag bit is set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
ous stream of pulses is generated, indefinitely.
The OCxIF flag is set on each OCxRS-TMRy
compare match event.
Setup for Continuous Output
Pulse Generation
dsPIC33F
DS70165E-page 171