DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 184

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

dsPIC33F
15.10.2
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge-Aligned mode – when PTMR is zero
• Center-Aligned modes – when PTMR is zero and
15.11 PWM Output and Polarity Control
There are three device Configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL Configuration bit
• LPOL Configuration bit
• PWMPIN Configuration bit
These three bits in the FPOR Configuration register
(see Section 23.0 “Special Features”) work in con-
junction with the eight PWM Enable bits (PENxH<4:1>,
PENxL<4:1>) located in the PWMCON1 SFR. The
Configuration bits and PWM Enable bits ensure that
the PWM pins are in the correct states after a device
Reset occurs. The PWMPIN configuration fuse allows
the PWM module outputs to be optionally enabled on a
device Reset. If PWMPIN = 0, the PWM outputs will be
driven to their inactive states at Reset. If PWMPIN = 1
(default), the PWM outputs will be tri-stated. The HPOL
bit specifies the polarity for the PWMxH outputs,
whereas the LPOL bit specifies the polarity for the
PWMxL outputs.
15.11.1
The PENxH<4:1> and PENxL<4:1> control bits in the
PWMCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a partic-
ular PWM output pin is not enabled, it is treated as a
general purpose I/O pin.
15.12 PWM Fault Pins
There are two Fault pins (FLTA and FLTB) associated
with the PWM module. When asserted, these pins can
optionally drive each of the PWM I/O pins to a defined
state.
DS70165E-page 182
the value of PTMR matches PTPER
OVERRIDE SYNCHRONIZATION
OUTPUT PIN CONTROL
Preliminary
15.12.1
The FLTACON and FLTBCON SFRs each have four
control bits that determine whether a particular pair of
PWM I/O pins is to be controlled by the Fault input pin.
To enable a specific PWM I/O pin pair for Fault
overrides, the corresponding bit should be set in the
FLTACON or FLTBCON register.
If all enable bits are cleared in the FLTACON or
FLTBCON register, then the corresponding Fault input
pin has no effect on the PWM module and the pin may
be used as a general purpose interrupt or I/O pin.
15.12.2
The FLTACON and FLTBCON Special Function
Registers have eight bits each that determine the state
of each PWM I/O pin when it is overridden by a Fault
input. When these bits are cleared, the PWM I/O pin is
driven to the inactive state. If the bit is set, the PWM
I/O pin will be driven to the active state. The active
and inactive states are referenced to the polarity
defined for each PWM I/O pin (HPOL and LPOL
polarity control bits).
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a Fault condition. The
PWMxH pin always has priority in the Complementary
mode so that both I/O pins cannot be driven active
simultaneously.
15.12.3
If both Fault input pins have been assigned to control a
particular PWM I/O pin, the Fault state programmed for
the Fault A input pin will take priority over the Fault B
input pin.
Note:
FAULT PIN ENABLE BITS
The Fault pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON/FLTBCON registers are
cleared, then the Fault pin(s) could be
used as general purpose interrupt pin(s).
Each Fault pin has an interrupt vector,
interrupt flag bit and interrupt priority bits
associated with it.
FAULT STATES
FAULT PIN PRIORITY
© 2007 Microchip Technology Inc.