DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 55

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TABLE 3-8:
TABLE 3-9:
TABLE 3-10:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
QEICON
DFLTCON
POSCNT
MAXCNT
Legend:
SFR Name
SFR Name
Name
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
Addr
01E0 CNTERR
01E2
01E4
01E6
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
.
Addr
0200
0202
0204
0206
0208
020A
020C
Addr
021A
021C
SFR
SFR
0210
0212
0214
0216
0218
Bit 15
QEI REGISTER MAP
I2C1 REGISTER MAP
I2C2 REGISTER MAP
—
ACKSTAT
ACKSTAT
Bit 15
I2CEN
Bit 15
I2CEN
—
—
—
—
—
—
—
—
—
—
Bit 14
—
—
TRSTAT
TRSTAT
Bit 14
Bit 14
QEISIDL
—
—
—
—
—
—
—
—
—
—
—
—
Bit 13
—
I2CSIDL
I2CSIDL
Bit 13
Bit 13
Bit 12 Bit 11
INDX
—
—
—
—
—
—
—
—
—
—
—
—
—
UPDN
SCLREL
SCLREL
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 10
IMV<1:0>
IPMIEN
IPMIEN
Bit 11
Bit 11
—
—
—
—
—
—
QEIM<2:0>
—
—
—
—
—
—
Bit 9
Bit 10
A10M
Bit 10
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
CEID
Bit 8
Maximum Count<15:0>
Position Counter<15:0>
DISSLW
GCSTAT
GCSTAT
QEOUT
DISSLW
SWPAB PCDOUT
Bit 9
Bit 9
Bit 7
—
—
—
—
—
—
ADD10
SMEN
ADD10
Bit 8
SMEN
Bit 8
Bit 6
—
—
—
—
QECK<2:0>
IWCOL
GCEN
TQGATE
IWCOL
GCEN
Bit 7
Bit 7
Bit 5
STREN
STREN
I2COV
I2COV
Bit 6
Bit 6
Bit 4
TQCKPS<1:0>
Address Mask Register
Address Mask Register
ACKDT
ACKDT
Baud Rate Generator Register
Baud Rate Generator Register
Address Register
Address Register
Bit 5
Bit 5
D_A
D_A
Bit 3
—
ACKEN
ACKEN
Transmit Register
Receive Register
Transmit Register
Bit 4
Receive Register
Bit 4
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
P
Bit 2
—
RCEN
RCEN
Bit 3
Bit 3
Bit 1
S
S
—
Bit 2
R_W
Bit 2
R_W
PEN
PEN
Bit 0
—
RSEN
RSEN
Bit 1
RBF
Bit 1
RBF
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
Reset State
Bit 0
SEN
Bit 0
TBF
SEN
TBF
Resets
Resets
0000
00FF
0000
1000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All