DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 291

• Manufacturer Part Number: DSPIC33FJ64MC510T-I/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.0
dsPIC33F devices include several features intended to
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
23.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
TABLE 23-1:
© 2007 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF8004
0xF8006
0xF8008
0xF800A
0xF800C
0xF800E
0xF8010
0xF8012
0xF8014
0xF8016
Note 1:
Address
Note:
2:
3:
4:
SPECIAL FEATURES
Configuration Bits
FGS
FOSCSEL
FOSC
FWDT
FPOR
RESERVED3
FUID0
FUID1
FUID2
FUID3
On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX), these bits are reserved (read as ‘1’ and
must be programmed as ‘1’).
These reserved bits read as ‘1’ and must be programmed as ‘1’.
Unimplemented bits are read as ‘0’.
This reserved bit is a read-only copy of the GCP bit.
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Name
DEVICE CONFIGURATION REGISTER MAP
PWMPIN
FWDTEN
IESO
Bit 7
—
FCKSM<1:0>
RBS<1:0>
RSS<1:0>
(1)
HPOL
WINDIS
Bit 6
—
—
(1)
Preliminary
LPOL
TEMP
Bit 5
—
—
—
—
—
(1)
The device Configuration register map is shown in
Table 23-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
Bit 4
Reserved
—
—
—
—
—
—
(2)
Bit 3
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC
WDTPOST<3:0>
GSS1
Bit 2
1111’. This makes them
dsPIC33F
FPWRT<2:0>
DS70165E-page 289
GSS0
POSCMD<1:0>
Bit 1
GWRP
BWRP
SWRP
Bit 0