DSPIC33FJ64MC510T-I/PT Microchip Technology, DSPIC33FJ64MC510T-I/PT Datasheet - Page 159

IC DSPIC MCU/DSP 64K 100TQFP

DSPIC33FJ64MC510T-I/PT

Manufacturer Part Number
DSPIC33FJ64MC510T-I/PT
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510T-I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ64MC510T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ64MC510T-I/PT
Manufacturer:
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Quantity:
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9.0
The dsPIC33F devices provide the ability to manage
power consumption by selectively managing clocking
to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of cir-
cuits being clocked constitutes lower consumed power.
dsPIC33F devices can manage power consumption in
four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
dsPIC33F devices allow a wide range of clock frequen-
cies to be selected under application control. If the
system clock configuration is not locked, users can
choose low-power or high-precision oscillators by
simply changing the NOSC bits (OSCCON<10:8>).
The process of changing a system clock during
operation, as well as limitations to the process, are
discussed in more detail in Section 8.0 “Oscillator
Configuration”.
9.2
dsPIC33F devices have two special power-saving
modes that are entered through the execution of a
special PWRSAV instruction. Sleep mode stops clock
EXAMPLE 9-1:
© 2007 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note:
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
Instruction-Based Power-Saving
Modes
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
PWRSAV INSTRUCTION SYNTAX
; Put the device into SLEEP mode
; Put the device into IDLE mode
Preliminary
operation and halts all code execution. Idle mode halts
the CPU and code execution, but allows peripheral
modules to continue operation. The assembly syntax of
the PWRSAV instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
9.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
Note:
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
dsPIC33F
DS70165E-page 157

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