ST62T65CM6 | |
---|---|
Manufacturer Part Number | ST62T65CM6 |
Description | IC MCU 8BIT OTP/EPROM 28 PSOIC |
Manufacturer | STMicroelectronics |
Series | ST6 |
ST62T65CM6 datasheet |
|
Specifications of ST62T65CM6 | |||
---|---|---|---|
Core Processor | ST6 | Core Size | 8-Bit |
Speed | 8MHz | Connectivity | SPI |
Peripherals | LED, LVD, POR, WDT | Number Of I /o | 21 |
Program Memory Size | 3.8KB (3.8K x 8) | Program Memory Type | OTP |
Eeprom Size | 128 x 8 | Ram Size | 128 x 8 |
Voltage - Supply (vcc/vdd) | 3 V ~ 6 V | Data Converters | A/D 13x8b |
Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
Package / Case | 28-SOIC (7.5mm Width) | Controller Family/series | ST6 |
No. Of I/o's | 21 | Eeprom Memory Size | 128Byte |
Ram Memory Size | 128Byte | Cpu Speed | 8MHz |
No. Of Timers | 2 | Rohs Compliant | Yes |
Processor Series | ST62T6x | Core | ST6 |
Data Bus Width | 8 bit | Data Ram Size | 128 B |
Interface Type | SCI | Maximum Clock Frequency | 8 MHz |
Number Of Programmable I/os | 21 | Number Of Timers | 1 |
Operating Supply Voltage | 3 V to 6 V | Maximum Operating Temperature | + 125 C |
Mounting Style | SMD/SMT | Development Tools By Supplier | ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II |
Minimum Operating Temperature | - 40 C | On-chip Adc | 8 bit |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Other names | 497-2103-5 |
PrevNext
ST6255C ST6265C ST6265B
3.3 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors are located in Pro-
gram space (see
Table
7).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Table 7. Interrupt Vector Map
Interrupt Source
Priority
Interrupt source #0
1
Interrupt source #1
2
Interrupt source #2
3
Interrupt source #3
4
Interrupt source #4
5
3.3.1 Interrupt request
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
30/84
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
Vector Address
ate interrupt service routine is executed instead.
(FFCh-FFDh)
(FF6h-FF7h)
Table 8. Interrupt Option Register Description
(FF4h-FF5h)
(FF2h-FF3h)
GEN
(FF0h-FF1h)
ESB
LES
OTHERS
SET
Enable all interrupts
CLEARED
Disable all interrupts
Rising edge mode on inter-
SET
rupt source #2
Falling edge mode on inter-
CLEARED
rupt source #2
Level-sensitive mode on in-
SET
terrupt source #1
Falling edge mode on inter-
CLEARED
rupt source #1
NOT USED
Related parts for ST62T65CM6 | |||
---|---|---|---|
Part Number | Description | Manufacturer | Datasheet |
![]() |
IC MCU 8BIT W/ADC 28-PDIP | STMicroelectronics |
|
![]() |
Microcontrollers (MCU) OTP EPROM 4K SPI | STMicroelectronics |
|
![]() |
8-bit Otp/eprom Mcus With A/d Converter, Safe Reset, Auto-reload Timer, Eeprom And Spi | STMicroelectronics |
|
![]() |
8-bit Otp/eprom/fastrom Mcus With A/d Converter, Safe Reset, Auto-reload Timer, Eeprom And Spi | STMicroelectronics |
|
![]() |
8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer, Eeprom And Spi | STMicroelectronics |
|
![]() |
Microcontrollers (MCU) OTP EPROM 2K No Intf | STMicroelectronics |
|
![]() |
IC MCU 8BIT W/ADC 16-SOIC | STMicroelectronics |
|
![]() |
IC MCU 8BIT W/ADC 20-PDIP | STMicroelectronics |
|
![]() |
IC MCU 8BIT OTP/EPROM 20 PSOIC | STMicroelectronics |
|
![]() |
MCU 8-Bit ST6 CISC 3884Byte EPROM 5V 20-Pin SO | STMicroelectronics | |
![]() |
IC MCU 8BIT W/ADC 16-SOIC | STMicroelectronics |
|
![]() |
8BIT MCU OTP 2K+EEPROM, 62T62, DIP | STMicroelectronics |
|
![]() |
8-bit Otp/eprom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom | STMicroelectronics |
|
![]() |
8-bit Otp/eprom/fastrom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom | STMicroelectronics |
|
![]() |
8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer And Eeprom | STMicroelectronics |
|