IC MCU 8BIT OTP/EPROM 28 PSOIC

ST62T65CM6

Manufacturer Part NumberST62T65CM6
DescriptionIC MCU 8BIT OTP/EPROM 28 PSOIC
ManufacturerSTMicroelectronics
SeriesST6
ST62T65CM6 datasheet
 


Specifications of ST62T65CM6

Core ProcessorST6Core Size8-Bit
Speed8MHzConnectivitySPI
PeripheralsLED, LVD, POR, WDTNumber Of I /o21
Program Memory Size3.8KB (3.8K x 8)Program Memory TypeOTP
Eeprom Size128 x 8Ram Size128 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 13x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-SOIC (7.5mm Width)Controller Family/seriesST6
No. Of I/o's21Eeprom Memory Size128Byte
Ram Memory Size128ByteCpu Speed8MHz
No. Of Timers2Rohs CompliantYes
Processor SeriesST62T6xCoreST6
Data Bus Width8 bitData Ram Size128 B
Interface TypeSCIMaximum Clock Frequency8 MHz
Number Of Programmable I/os21Number Of Timers1
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-2103-5
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INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Table 20. Conditional Branch Instructions
Instruction
Branch If
JRC e
C = 1
JRNC e
C = 0
JRZ e
Z = 1
JRNZ e
Z = 0
JRR b, rr, ee
Bit = 0
JRS b, rr, ee
Bit = 1
:
Notes
b.
3-bit address
e.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
Table 21. Bit Manipulation Instructions
Instruction
Addressing Mode
SET b,rr
Bit Direct
RES b,rr
Bit Direct
Notes:
b.
3-bit address;
rr.
Data space register;
Table 22. Control Instructions
Instruction
Addressing Mode
NOP
Inherent
RET
Inherent
RETI
Inherent
STOP (1)
Inherent
WAIT
Inherent
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
.
Affected
*.
Not Affected
Table 23. Jump & Call Instructions
Instruction
Addressing Mode
CALL abc
Extended
JP abc
Extended
Notes:
abc. 12-bit address;
* .
Not Affected
ST6255C ST6265C ST6265B
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Bytes
Cycles
1
2
1
2
1
2
1
2
3
5
3
5
rr.
Data space register
. Affected. The tested bit is shifted into carry.
* .
Not Affected
Bytes
Cycles
2
4
2
4
* . Not<M> Affected
Bytes
Cycles
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2
1
2
1
2
1
2
1
2
Bytes
Cycles
2
4
2
4
Flags
Z
C
*
*
*
*
*
*
*
*
*
*
Flags
Z
C
*
*
*
*
Flags
Z
C
*
*
*
*
*
*
*
*
Flags
Z
C
*
*
*
*
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