IC MCU 8BIT OTP/EPROM 28 PSOIC

ST62T65CM6

Manufacturer Part NumberST62T65CM6
DescriptionIC MCU 8BIT OTP/EPROM 28 PSOIC
ManufacturerSTMicroelectronics
SeriesST6
ST62T65CM6 datasheet
 


Specifications of ST62T65CM6

Core ProcessorST6Core Size8-Bit
Speed8MHzConnectivitySPI
PeripheralsLED, LVD, POR, WDTNumber Of I /o21
Program Memory Size3.8KB (3.8K x 8)Program Memory TypeOTP
Eeprom Size128 x 8Ram Size128 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 13x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-SOIC (7.5mm Width)Controller Family/seriesST6
No. Of I/o's21Eeprom Memory Size128Byte
Ram Memory Size128ByteCpu Speed8MHz
No. Of Timers2Rohs CompliantYes
Processor SeriesST62T6xCoreST6
Data Bus Width8 bitData Ram Size128 B
Interface TypeSCIMaximum Clock Frequency8 MHz
Number Of Programmable I/os21Number Of Timers1
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-2103-5
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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)
SPI DIV Register (DIV)
Address: E1h — Read/Write
Reset status: 00h
7
SPINT
DOV6
DIV5
DIV4
DIV3
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register is set.
Bit 7 = SPINT: Interrupt Flag. If SPIE bit=1, SPINT
is automatically set to one by the SPI at the end of
a transmission or reception and an interrupt re-
quest can be generated depending on the state of
the interrupt mask bit in the MOD control register.
This bit is write and read and must be cleared by
user software at the end of the interrupt service
routine.
Bit 6-3 = DIV6-DIV3: Burst Mode Bit Clock Period
Selection. Define the number of shift register bits
that are transmitted or received in a frame. The
available selections are listed in
normal maximum setting is 8 bits, since the shift
register is 8 bits wide. Note that by setting a great-
er number of bits, in conjunction with the SPIN bit
in the MOD register, unwanted data bits may be fil-
tered from the data stream.
Bit 2-0 = CD2-CD0: Base/Bit Clock Rate Selec-
tion. Define the division ratio between the core
clock (f
divided by 13) and the clock supplied to
INT
the Shift Register in Master mode.
Table 16. Base/Bit Clock Ratio Selection
CD2-CD0
Divide Ratio (decimal)
0
0
0
Divide by 1
0
0
1
Divide by 2
0
1
0
Divide by 4
0
1
1
Divide by 8
1
0
0
Divide by 16
1
0
1
Divide by 32
1
1
0
Divide by 64
1
1
1
Divide by 256
Note: For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
Data setup time on Sin is typically 250ns min, while
data hold time is typically 50ns min.
Table 17. Burst Mode Bit Clock Periods
DIV6-DIV3
0
0
0
0
0
0
0
CD2
CD1
CD0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
SPI Data/Shift Register (SPIDSR)
Address: E0h — Read/Write
Table
17. The
Reset status: XXh
7
D7
SPIDSR is read/write, however write access is not
allowed if the SPRUN bit of Mode Control register
is set to one.
Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA bits. The affect
of these setting is shown in the following diagrams.
The Shift Register transmits and receives the Most
Significant Bit first.
Bit 7-0 = DSR7-DSR0: Data Bits. These are the
SPI shift register data bits.
Miscellaneous Register (MISCR)
Address: DDh — Write only
Reset status: xxxxxxxb
7
-
Bit 7-1 = D7-D1: Reserved.
Bit 0 = D0: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
ST6255C ST6265C ST6265B
Number of bits sent
0
0
Reserved (not to be used)
0
1
1
0
2
1
1
1
3
0
0
4
0
1
5
1
0
6
1
1
7
0
0
8
0
1
9
1
0
10
1
1
11
Refer to the
0
0
12
description of the
0
1
13
DIV6-DIV3 bits in
1
0
14
the DIV Register
1
1
15
D6
D5
D4
D3
D2
-
-
-
-
-
0
D1
D0
0
-
D0
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