IC MCU 8BIT OTP/EPROM 28 PSOIC

ST62T65CM6

Manufacturer Part NumberST62T65CM6
DescriptionIC MCU 8BIT OTP/EPROM 28 PSOIC
ManufacturerSTMicroelectronics
SeriesST6
ST62T65CM6 datasheet
 


Specifications of ST62T65CM6

Core ProcessorST6Core Size8-Bit
Speed8MHzConnectivitySPI
PeripheralsLED, LVD, POR, WDTNumber Of I /o21
Program Memory Size3.8KB (3.8K x 8)Program Memory TypeOTP
Eeprom Size128 x 8Ram Size128 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 13x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-SOIC (7.5mm Width)Controller Family/seriesST6
No. Of I/o's21Eeprom Memory Size128Byte
Ram Memory Size128ByteCpu Speed8MHz
No. Of Timers2Rohs CompliantYes
Processor SeriesST62T6xCoreST6
Data Bus Width8 bitData Ram Size128 B
Interface TypeSCIMaximum Clock Frequency8 MHz
Number Of Programmable I/os21Number Of Timers1
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-2103-5
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ST6255C ST6265C ST6265B
INTERRUPTS (Cont’d)
3.3.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
-
LES
ESB
GEN
-
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 9. Interrupt Requests and Mask Bits
Peripheral
Register
GENERAL
IOR
TIMER
TSCR1
A/D CONVERTER
ADCR
AR TIMER
ARMC
SPI
SPIMOD
Port PAn
ORPA-DRPA
Port PBn
ORPB-DRPB
Port PCn
ORPC-DRPC
32/84
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
0
modes.
This register is cleared on reset.
-
-
-
3.3.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the
bit to enable/disable the interrupt request.
Address
Mask bit
Register
C8h
GEN
D4h
ETI
D1h
EAI
OVIE
D5h
CPIE
EIE
E2h
SPIE
C0h-C4h
ORPAn-DRPAn
C1h-C5h
ORPBn-DRPBn
C2h-C6h
ORPCn-DRPCn
Table 9
with associated mask
Interrupt
Masked Interrupt Source
All Interrupts, excluding NM
I
TMZ: TIMER Overflow
Vector 4
EOC: End of Conversion
Vector 4
OVF: AR TIMER Overflow
CPF: Successful compare
Vector 3
EF: Active edge on ARTIMin
SPRUN: End of Transmission
Vector 2
PAn pin
Vector 1
PBn pin
Vector 1
PCn pin
Vector 2
vector